The present invention generally relates to computer architectures, and particularly to an extended memory system for a computer based upon the Harvard architecture.
A computer which includes the following two characteristics is generally referred to as having a "Harvard" architecture. Namely, the computer will be designed with separate instruction and data stores, and independent buses will be provided to enable the central processing unit ("CPU") of the computer to communicate separately with each of these stores. This is in contrast to a "yon Neumann" or "Princeton" based computer architecture, which generally employs the same physical store for both instructions and data, and a single bus structure for communication with the CPU. Various approaches have been taken to designing a microcomputer or microprocessor with a Harvard architecture, as represented by the following patents: Yasui et al. U.S. Pat. No. 5,034,887, issued on Jul. 23, 1991, entitled "Microprocessor With Harvard Architecture"; Portanova et al. U.S. Pat. No. 4,992,934, issued on Feb. 12, 1991, entitled "Reduced Instruction Set Computing Apparatus And Methods"; Mehrgardt et al. U.S. Pat. No. 4,964,046, issued on Oct. 16, 1990, entitled "Harvard Architecture Microprocessor With Arithmetic Operations And Control Tasks For Data Transfer Handled Simultaneously"; and Simpon U.S. Pat. No. 4,494,187, issued on Jan. 15, 1985, entitled "Microcomputer With High Speed Program Memory". Additionally, it should be noted that the Intel i860 64-bit microcomputer has been described as having an on-board Harvard architecture, due to the provision of separate instruction and data cache paths. In this regard, a description of the Intel i860 chip design may be found in i60 Microprocessor Architecture, by Neal Margulis, Osborne McGraw-Hill, 1990.
The use of separate instruction and data communication paths in a Harvard architecture machine effectively increases the overall speed of the computer by enabling an instruction to be accessed at the same time that data for this or another instruction is accessed. In the context of programmed operations, the instruction is usually referred to as the "opcode" (the operation code), and the data is referred to the "operand". While the benefit in speed of using the Harvard architecture is significant, the full potential of a machine based upon the Harvard architecture, has yet to be realized. More specifically, it is believed that substantial advantages may be achieved by addressing the nature, roles and potential cooperation between separate memory stores in a machine which is based upon the Harvard architecture.
Accordingly, it is a principal objective of the present invention to provide a unique memory system which significantly extends the capability of the Harvard architecture.
It is another objective of the present invention to provide an extended memory system which reduces the amount of memory space required to store a computer program.
It is a further objective of the present invention to provide an extended memory system which enables at least two different memory accessing procedures to be utilized.
It is an additional objective of the present invention to provide an extended memory system which reduces the time required for often repeated memory operations.
It is also an objective of the present invention to provide an extended memory system which more effectively utilizes a desired data structure.
It is yet another objective of the present invention to provide an extended memory system which is particularly advantageous in a process control computer.